Summary

A carbon nanotube (CNT) is a tube made of carbon with diameters measured in nanometres. A carbon nanotube field-effect transistor (CNTFET) is a field-effect transistor that utilises carbon nanotubes as the channel material instead of silicon used in the metal–oxide–semiconductor field-effect transistors (MOSFET). The most common semiconductor fabrication process, complementary metal–oxide–semiconductor (CMOS) uses MOSFETs as the logic functions. CNTFETs exhibit better electrical and thermal properties than silicon and so are considered candidates to deliver performance improvement beyond 2nm nodes.

Viability (3)

CNTFET progress has been slow since the discovery of carbon nanotubes in 1991. The first gate was demonstrated in 1998 and the first circuit in 2006. CNTFETs were slated as a replacement for planar transistors in the late 00s, but finFETs “3D transistors” were selected because the technology and fabrication processes were more mature. In 2022, there are still no commercially available CNTFETs with the major R&D challenge of synthesizing high-purity nanotubes without variations and integrating them into chips. The main barrier is that the industry-standard incubation process doesn’t work well with carbon nanotubes, which tend to be deposited on wafers in random orientation and/or too few carbon nanotubes successfully stick to the wafer. New methods such as dry cycling and ACE (artificial concentration through evaporation) have demonstrated viability in a fab setting and now require further scaling work.

Drivers (5)

The drive to continue to deliver on Moore’s Law post 2nm is driving R&D. At 3nm/2nm from 2023/2024, finFETs will be replaced with gate-all-around (GAA) FETs for high performance applications. But the roadmap stops beyond 2nm as any further reduction in size would give rise to tunnel effects thus degrading the whole performances. Complementary FET (CFET) are an option which basically fold wires on top of each other instead of simply stacking with GAA FETs. But this would be an incremental improvement versus the orders of magnitude improvement possible with CNTFETs if fabrication hurdles can be overcome.

Novelty (3)

CNTFET compete with improvements in MOSFET technology such as GAA nanosheets and forksheets and CFET designs at least for the until 2036. Relative to silicon, carbon nanotubes have two main advantages: higher current carrier mobility providing a superior drive current density and ability to manufacture at near-room temperatures. With higher carrier mobility, It is expected that with the same power consumption, they will be three times faster than silicon-based transistors. Unlike silicon-based transistors, which are made at temperatures around 450 to 500 degrees Celsius, fabricated at lower temperatures, as are memory chips, so ideal to build chips with highly dense connections between memory and logic reducing latency and power consumption. Gallium oxide is an alternative to carbon nanotubes as it has a high critical electric-field strength but very poor thermal conductivity.

Diffusion (3)

Relative to alternative IC alternatives, CNTFETs have been in consideration to replace CMOS for a long time. All major foundries have projects exploring the fabrication of carbon nanotubes. There are still challenges to overcome such as the incubation challenge and tooling is so specific to current CMOS fabrication that foundries will signpost a move to carbon nanotubes 5 years or more before production. Signalling demand will give supply time to scale up especially as most demand today is for multi-walled technology not the single-wall technology needed for CNTFETs. It will also allow the industry to standardise around a common configuration whether back-gated, top-gated, or wrap around.

Impact (3) Low certainty

High impact scenario is carbon nanotubes replacing the silicon transistor. For all the highly impactful technologies from Whole Brain Emulation, Brain-Computer Interfaces and Quantum Hardware, they all rely on the continued performance improvements of the computing industry. From 2035 we run out of rope with silicon at atomic CFETs and carbon nanotubes are the most likely candidate to continue performance gains. Performance gains will come from new architectures, reconfigurability, and unconventional approaches, all of which can in theory benefit from using CNT instead of CMOS. A low impact scenario sees scaling carbon nanotubes proving to be too difficult and costly to fabricate at scale and incremental advances in MOSFET with GAA and CFET taking us into the late 2030s. Quantum Chemistry Software and machine learning push developments on material science finding a room temperature superconductor for example.

Timing (2030+) High certainty

We already know the semiconductor roadmap at 2nm is GAA nanosheets, at A10 and A7 it will be GAA forksheets, at A5, A3 CFET, and then A2 in 2036 is atomic CFET. CNTFET are on the radar of all leading foundries and any move would be signposted 5 years in advance minimum. With a pretty set pipeline at least into 2030 it’s unlikely CNTFETs will arrive before 2030. it’s hard to imagine a catalyst impacting these timelines because the investment costs, economies of scale and consolidated market structure make fast change challenging.